1. Field of the Invention
The present invention relates to a semiconductor stack package which can operate at a high speed by noise reduction.
Priority is claimed on Japanese Patent Application No. 2007-199695, filed Jul. 31, 2007, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In a known structure of semiconductor stack packages, semiconductor chips or semiconductor packages are stacked. In accordance with recent improvements in high-density packaging, further size-reduction or thing is required, and various structures for stacking semiconductor chips have been proposed by manufacturing companies.
In the semiconductor chip structure of a first known example of semiconductor stack chips, two semiconductor chips are stacked in a manner such that the back faces thereof face each other. A lead frame is provided at each of the upper and lower faces of the relevant stack structure, and the circuits of each semiconductor chip and the corresponding lead frame are connected by means of bonding, wherein the upper and lower lead frames branch from a single lead (see Patent Document 1).
In the stack package of a second known example of semiconductor stack chips, two semiconductor chips are integrated in a manner such that back faces thereof face each other, and the integrated body is embedded in a sealing material. A printed substrate layer is also embedded in the sealing material, where it separates from the printed substrate layer and semiconductor chips. The printed substrate layer is connected to an external lead, and the printed substrate layer and bonding pads of the semiconductor chips are connected to each other via bonding lines, so as to strengthen GND lines and power supply lines (see Patent Document 2).
In the semiconductor chip stack structure of a third known example of semiconductor stack chips, a first semiconductor chip and a second semiconductor chip are stacked via a paddle in which a flexible circuit is stacked on each of the upper and lower surfaces thereof. Terminals of each chip are connected to the relevant flexible circuit, and also connected to external leads by using long wires (see Patent Document 3).
In another known semiconductor chip structure in which upper and lower semiconductor chips are stacked on a printed wiring (or circuit) board, the circuit face of the lower semiconductor chip faces downward (i.e., faces the printed wiring board) while the upper semiconductor chip faces upward. Pads of the lower semiconductor chip are connected via wires to the lower face (i.e., opposite to the face on which the semiconductor chips are stacked) of the printed wiring board (see Patent Document 4).
FIG. 15 shows another generally-known example of semiconductor chip stack structures. In the structure, a spacer 102 is provided between upper and lower semiconductor chips 100a and 100b which are stacked on a printed wiring board 103. As electrode pads 104a and 104b of the semiconductor chips 100a and 100b are provided at periphery ends thereof, the pads can be connected to connection lands 103a on the printed wiring board 103 (on which the semiconductor chips 100a and 100b are provided) via relatively short wires 105. However, in a device in which electrode pads are arranged at the center of the relevant semiconductor chip (e.g., a general-purpose DRAM (dynamic random access memory)), a long wire is arranged from each electrode pad at the center of the chip to the outside of the chip, so as to connect the electrode pad to the corresponding connection land 103a of the relevant printed wiring board 103. Therefore, no spacer 102 as shown in FIG. 15 can be provided.
FIGS. 16A and 16B show examples of chip stack structures, in which electrode pads are provided at the center of the relevant semiconductor chips.
In the structure shown in FIG. 16A, semiconductor chips 108a and 108b are stacked on a printed wiring board 107 while they are surrounded by a sealing material 109. In addition to pads for signal transmission of the semiconductor chips 108a and 108b, electrode pads 110a and 110b for providing power supply and grounding are also connected to connection lands 107b, which are provided at a peripheral area of the printed wiring board 107, via long wires 112a and 112b. 
In the structure shown in FIG. 16B, semiconductor chips 115a and 115b are stacked on a printed wiring board 116. The circuit face of the lower semiconductor chip 115a faces downward, while the circuit face of the upper semiconductor chip 115b faces upward. The printed wiring board 116 has a through-hole 118 in which electrode pads 115c of the lower semiconductor chip 115a are positioned. In this structure, the electrode pads 115c are connected via the through-hole 118 to connection lands 116a, which are provided on the back face of the printed wiring board 116, by using short wires 117a, where wiring lines of circuits on the printed wiring board 116 are thicker than the diameter of each wire 117a.     Patent Document 1: Japanese Unexamined Patent Application, First Publication No. H11-163255.    Patent Document 2: Japanese Unexamined Patent Application, First Publication No. H11-289043.    Patent Document 3: Published Japanese Translation, No. H11-502063, of PCT International Publication, No. WO96/28860.    Patent Document 4: Japanese Unexamined Patent Application, First Publication No. 2001-85609.
In each upper semiconductor chip (108b or 115b) of the chip stack structures shown in FIGS. 16A and 16B, not only pads for transmitting signals and also electrode pads for providing power supply and grounding are connected to the connection lands (107a or 116b) provided on the printed wiring board (107 or 116) via long wires (112b or 117b). Therefore, the relevant inductance and resistance (i.e., LR) increase, which may cause noises or voltage drops, and prevent high-speed operation.
Also in the structure disclosed in Patent Document 4, electrode pads of the upper semiconductor chip are connected to connection lands, which are provided at the periphery of the relevant printed wiring board, via long wires. Therefore, the inductance and resistance of the power supply and grounding increase, which may cause noises or voltage drops, and prevent high-speed operations.